PowerPC Features (Debugging with GDB)
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G.5.11 PowerPC Features
The ‘org.gnu.gdb.power.core
’ feature is required for PowerPC targets. It should contain registers ‘r0
’ through ‘r31
’, ‘pc
’, ‘msr
’, ‘cr
’, ‘lr
’, ‘ctr
’, and ‘xer
’. They may be 32-bit or 64-bit depending on the target.
The ‘org.gnu.gdb.power.fpu
’ feature is optional. It should contain registers ‘f0
’ through ‘f31
’ and ‘fpscr
’.
The ‘org.gnu.gdb.power.altivec
’ feature is optional. It should contain registers ‘vr0
’ through ‘vr31
’, ‘vscr
’, and ‘vrsave
’. GDB will define pseudo-registers ‘v0
’ through ‘v31
’ as aliases for the corresponding ‘vrX
’ registers.
The ‘org.gnu.gdb.power.vsx
’ feature is optional. It should contain registers ‘vs0h
’ through ‘vs31h
’. GDB will combine these registers with the floating point registers (‘f0
’ through ‘f31
’) and the altivec registers (‘vr0
’ through ‘vr31
’) to present the 128-bit wide registers ‘vs0
’ through ‘vs63
’, the set of vector-scalar registers for POWER7. Therefore, this feature requires both ‘org.gnu.gdb.power.fpu
’ and ‘org.gnu.gdb.power.altivec
’.
The ‘org.gnu.gdb.power.spe
’ feature is optional. It should contain registers ‘ev0h
’ through ‘ev31h
’, ‘acc
’, and ‘spefscr
’. SPE targets should provide 32-bit registers in ‘org.gnu.gdb.power.core
’ and provide the upper halves in ‘ev0h
’ through ‘ev31h
’. GDB will combine these to present registers ‘ev0
’ through ‘ev31
’ to the user.
The ‘org.gnu.gdb.power.ppr
’ feature is optional. It should contain the 64-bit register ‘ppr
’.
The ‘org.gnu.gdb.power.dscr
’ feature is optional. It should contain the 64-bit register ‘dscr
’.
The ‘org.gnu.gdb.power.tar
’ feature is optional. It should contain the 64-bit register ‘tar
’.
The ‘org.gnu.gdb.power.ebb
’ feature is optional. It should contain registers ‘bescr
’, ‘ebbhr
’ and ‘ebbrr
’, all 64-bit wide.
The ‘org.gnu.gdb.power.linux.pmu
’ feature is optional. It should contain registers ‘mmcr0
’, ‘mmcr2
’, ‘siar
’, ‘sdar
’ and ‘sier
’, all 64-bit wide. This is the subset of the isa 2.07 server PMU registers provided by GNU/Linux.
The ‘org.gnu.gdb.power.htm.spr
’ feature is optional. It should contain registers ‘tfhar
’, ‘texasr
’ and ‘tfiar
’, all 64-bit wide.
The ‘org.gnu.gdb.power.htm.core
’ feature is optional. It should contain the checkpointed general-purpose registers ‘cr0
’ through ‘cr31
’, as well as the checkpointed registers ‘clr
’ and ‘cctr
’. These registers may all be either 32-bit or 64-bit depending on the target. It should also contain the checkpointed registers ‘ccr
’ and ‘cxer
’, which should both be 32-bit wide.
The ‘org.gnu.gdb.power.htm.fpu
’ feature is optional. It should contain the checkpointed 64-bit floating-point registers ‘cf0
’ through ‘cf31
’, as well as the checkpointed 64-bit register ‘cfpscr
’.
The ‘org.gnu.gdb.power.htm.altivec
’ feature is optional. It should contain the checkpointed altivec registers ‘cvr0
’ through ‘cvr31
’, all 128-bit wide. It should also contain the checkpointed registers ‘cvscr
’ and ‘cvrsave
’, both 32-bit wide.
The ‘org.gnu.gdb.power.htm.vsx
’ feature is optional. It should contain registers ‘cvs0h
’ through ‘cvs31h
’. GDB will combine these registers with the checkpointed floating point registers (‘cf0
’ through ‘cf31
’) and the checkpointed altivec registers (‘cvr0
’ through ‘cvr31
’) to present the 128-bit wide checkpointed vector-scalar registers ‘cvs0
’ through ‘cvs63
’. Therefore, this feature requires both ‘org.gnu.gdb.power.htm.altivec
’ and ‘org.gnu.gdb.power.htm.fpu
’.
The ‘org.gnu.gdb.power.htm.ppr
’ feature is optional. It should contain the 64-bit checkpointed register ‘cppr
’.
The ‘org.gnu.gdb.power.htm.dscr
’ feature is optional. It should contain the 64-bit checkpointed register ‘cdscr
’.
The ‘org.gnu.gdb.power.htm.tar
’ feature is optional. It should contain the 64-bit checkpointed register ‘ctar
’.
Next: RISC-V Features, Previous: OpenRISC 1000 Features, Up: Standard Target Features [Contents][Index]