MIPS Features (Debugging with GDB)
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G.5.6 MIPS Features
The ‘org.gnu.gdb.mips.cpu
’ feature is required for MIPS targets. It should contain registers ‘r0
’ through ‘r31
’, ‘lo
’, ‘hi
’, and ‘pc
’. They may be 32-bit or 64-bit depending on the target.
The ‘org.gnu.gdb.mips.cp0
’ feature is also required. It should contain at least the ‘status
’, ‘badvaddr
’, and ‘cause
’ registers. They may be 32-bit or 64-bit depending on the target.
The ‘org.gnu.gdb.mips.fpu
’ feature is currently required, though it may be optional in a future version of GDB. It should contain registers ‘f0
’ through ‘f31
’, ‘fcsr
’, and ‘fir
’. They may be 32-bit or 64-bit depending on the target.
The ‘org.gnu.gdb.mips.dsp
’ feature is optional. It should contain registers ‘hi1
’ through ‘hi3
’, ‘lo1
’ through ‘lo3
’, and ‘dspctl
’. The ‘dspctl
’ register should be 32-bit and the rest may be 32-bit or 64-bit depending on the target.
The ‘org.gnu.gdb.mips.linux
’ feature is optional. It should contain a single register, ‘restart
’, which is used by the Linux kernel to control restartable syscalls.