Gdb/ARC-Features
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G.5.2 ARC Features
ARC processors are so configurable that even core registers and their numbers
are not predetermined completely. Moreover, flags and PC
registers, which are important to GDB, are not “core” registers in
ARC. Therefore, there are two features that their presence is mandatory:
‘org.gnu.gdb.arc.core
’ and ‘org.gnu.gdb.arc.aux
’.
The ‘org.gnu.gdb.arc.core
’ feature is required for all targets. It must
contain registers:
- - ‘
r0
’ through ‘r25
’ for normal register file targets. - - ‘
r0
’ through ‘r3
’, and ‘r10
’ through ‘r15
’ for reduced register file targets. - - ‘
gp
’, ‘fp
’, ‘sp
’, ‘r30
’21, ‘blink
’, ‘lp_count
’, ‘pcl
’.
In case of an ARCompact target (ARCv1 ISA), the ‘org.gnu.gdb.arc.core
’
feature may contain registers ‘ilink1
’ and ‘ilink2
’. While in case
of ARC EM and ARC HS targets (ARCv2 ISA), register ‘ilink
’ may be present.
The difference between ARCv1 and ARCv2 is the naming of registers 29th
and 30th. They are called ‘ilink1
’ and ‘ilink2
’ for ARCv1 and
are optional. For ARCv2, they are called ‘ilink
’ and ‘r30
’ and only
‘ilink
’ is optional. The optionality of ‘ilink*
’ registers is
because of their inaccessibility during user space debugging sessions.
Extension core registers ‘r32
’ through ‘r59
’ are optional and their
existence depends on the configuration. When debugging GNU/Linux applications,
i.e. user space debugging, these core registers are not available.
The ‘org.gnu.gdb.arc.aux
’ feature is required for all ARC targets. Here
is the list of registers pertinent to this feature:
- - mandatory: ‘
pc
’ and ‘status32
’. - - optional: ‘
lp_start
’, ‘lp_end
’, and ‘bta
’.